Cypress Semiconductor /psoc63 /SRSS /CLK_PLL_CONFIG[8]

Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 … 112: divide by 112

112: illegal (undefined behavior)

Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 … 20: divide by 20 others: illegal (undefined behavior)

Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. … 16: divide by 16. Suitable for direct usage as HFCLK source.

16: illegal (undefined behavior)

VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)

Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.

0 (AUTO): Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.

1 (AUTO1): Same as AUTO

2 (PLL_REF): Select PLL reference input (bypass mode). Ignores lock indicator

3 (PLL_OUT): Select PLL output. Ignores lock indicator.

Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1.

Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV)

0: Block is disabled 1: Block is enabled